Insulating layers on different semiconductor materials

ABSTRACT

A semiconductor structure is provided that includes a substrate having disposed thereon a silicon layer and a silicon germanium layer. An insulator is disposed between the silicon layer and the silicon germanium layer. An optional silicon nitride film is disposed conformally on the silicon layer and the silicon germanium layer, and a SiO 2 layer disposed on the optional silicon nitride film or on the silicon layer and the silicon germanium layer, when the optional silicon nitride film is not present.

RELATED APPLICATIONS

This application is a divisional of U.S. Ser. No. 12/685,332, filed Jan.11, 2010, the entire contents of which are incorporated herein byreference.

FIELD OF THE INVENTION

The present invention relates to methods of creating insulating layersfor semiconductor device structures, and particularly for field effecttransistor structures formed on a same substrate. The present inventionrelates also to semiconductor structures created during the methods.

BACKGROUND OF THE INVENTION

High performance logic device structures often include embedded SiGechannels in the pFETs while the nFETs are constructed on conventionalsingle crystal substrates. To construct multiple gate oxides (so calleddouble gate architectures) on embedded SiGe channels and on Si channelsrequires that the gate insulators/dielectrics be deposited, for example,by means of chemical vapor deposition (CVD). CVD techniques are used inorder to construct devices with comparable physical thicknesses. If thedouble gate oxides are constructed by means of thermal oxidation (in amanner consistent with non-SiGe channel technologies), then thediffering oxidation rates of the SiGe and Si will result in devices withdifferent characteristics (Tiny, Vt, Ion/Ioff etc.). These differentcharacteristics are often problematic.

In most cases, the CVD oxides deposited on SiGe channels are so called“high temperature oxides” or HTOs. HTOs can be deposited in eithersingle wafer or batch furnace type tools. HTOs are typically producedthrough a reaction of SiH4 or Si2H6 with N2O, O2 or H2O at reducedpressures such as 200 Torr and temperatures between 600° C. and 800° C.

It is often reported that HTO layers are of lower quality when comparedto SiO₂ films (layers) produced by means of thermal oxidation of singlecrystal substrates. The lower film quality is manifested in higher trapdensities (in the bulk of the film and the interface) which often leadsto reduced reliability metrics, e.g. Vbd, TDDB, NBTI, etc. This reducedreliability, therefore, generally precludes the use of HTOs in highperformance CMOS transistor applications.

SUMMARY OF THE INVENTION

The present invention is directed to processes for (methods of) creatinghigh quality SiO₂ films and interfaces in high performance CMOStechnologies which use SiGe (or some other semiconducting material suchas SiC, GaAs, etc.) which results in differing oxidation rates on then-FET region and p-FET region and, thereby, precludes the use ofconventional thermal oxidation to create the FET devices.

The inventive processes described through embodiments herein are basedon the deposition of a thin layer of a sacrificial material, e.g.,Si3N4. The thin layer is deposited in a continuous film ranging from asingle monolayer to any desired thickness. In the embodiments, thecontinuous film of the sacrificial material preferably is conformal withthe underlying materials. The sacrificial material is then oxidized to athickness which consumes (preferably, completely) the sacrificial filmbut does not oxidize more than ten (10) angstroms into the underlyingSiGe material. Because the gate dielectric is created by means of thethermal oxidation of the sacrificial material, the composition of thefinished (oxidized in this case) material is not dictated by thetransport of, the ratio of, or the purity of process gasses, but ratherby: 1) the availability of Si in the starting material, and 2) thepresence of a suitable oxidant.

The inventors believe films and interfaces created according toembodiments of the present invention will be of a higher quality thanCVD deposited oxides (e.g., HTOs) and may be employed in integrationarrangements requiring multiple gate oxides disposed on channelsconstructed of dissimilar materials.

According to a preferred embodiment of the present invention, a methodof creating insulating layers on different semiconductor materialsincludes: providing a substrate having disposed thereon a first materialand a second material, the second material having a chemical compositiondifferent from the first material; non-epitaxially depositing acontinuous sacrificial layer of approximately constant thickness ontothe first material and the second material; and then converting thesacrificial layer into a layer consisting essentially of SiO₂ withoutoxidizing more than ten (10) angstroms into the second material. Morepreferably, the sacrificial layer is converted entirely into SiO₂without oxidizing any of the second material.

It is a principal object of the present invention to provide a method ofcreating oxides having at least approximately (±10%) equal or equalthicknesses on different semiconductor materials.

It is a further object of the present invention to provide such a methodthat is highly compatible with conventional methods/processes forproducing nFETs and pFETs on a same substrate.

Further and still other objects of the present invention will becomemore readily apparent when the following description is taken inconjunction with the drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional block diagram showing step one of apreferred embodiment of the present invention.

FIG. 2 is a cross-sectional block diagram showing step two of thepreferred embodiment.

FIG. 3 is a cross-sectional block diagram showing step three of thepreferred embodiment.

FIG. 4 is a cross-sectional block diagram showing step four of thepreferred embodiment.

FIG. 5 is a cross-sectional block diagram showing final gate structuresafter performing additional steps according to an additional preferredembodiment of the invention.

FIG. 6 is a cross-sectional block diagram showing a completed nFET and acompleted pFET after performing additional steps (spacer formation,source and drain implants, silicide formation) on the embodiment shownin FIG. 5.

FIG. 7 is a diagram showing characterization of the conversion of MLDSi3N4 to Si02 via radical oxygen.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS AND BEST MODE

Turning now to FIGS. 1-4, and FIG. 7, there is shown a preferredembodiment of the steps according to the present invention.

FIG. 1 shows a starting condition or step for the preferred embodiment.There is provided a semiconductor (e.g., bulk silicon) substrate 10having a first region such as a P-FET region 11 and a second region suchas an N-FET region 12. A silicon germanium channel region 13 is formedat the P-FET region and a silicon channel region 14 is formed at theN-FET region. The regions 13, 14 are formed by conventional CMOSmanufacturing process techniques. For example, region 14 is created bydry etching the starting substrate 10 to form the N-FET region. Region13 is created via an epitaxial growth of a silicon germanium film with adesired Ge concentration (typically 20%). Of course, other suitable Geconcentrations may be used.

In the preferred embodiment, the chemical composition of the region 14,for example, includes or preferably consists essentially of Si, whilethe chemical composition of the region 13 includes or preferablyconsists essentially of SiGe.

In FIG. 2, a continuous, sacrificial film 15 is deposited on both the Siand the SiGe channel regions 14, 13 after conventional shallow trenchisolation (STI) formation. FIG. 2 shows the deposition of a thinmolecular layer deposited (MLD) silicon nitride film havingapproximately (±10%) equal and constant thicknesses on both the nFET andpFET channel regions 14, 13. Preferably, the film 15 is conformal withthe regions 14, 13. Typical thicknesses of the film 15 range from about10 angstroms to about 50 angstroms. The MLD silicon nitride film 15 is“sacrificial” in the sense that the film 15 will be converted into ahigh quality SiO₂ having excellent reliability and interfacialqualities. This Si3N4 film 15 is deposited, for example, using thefollowing tool model “iRAD” commercially available from Tokyo ElectronLimited (TEL).

The embodiment disclosed herein uses MLD Si3N4 but can be performed wellwith other sacrificial materials which can be deposited sufficientlythin and continuous, and which can be converted to SiO₂ via knownthermal or plasma techniques. Such sacrificial materials include, forexample, amorphous silicon, polycrystalline silicon, or silicon carbide.Such other sacrificial materials can be deposited using tools such astool model “SinGen” commercially available from Applied Materials, Inc.(AMAT). Also, the thermal or plasma techniques can be performed usingtools such as tool model “Radiance” or “DPN” commercially available fromApplied Materials, Inc. (AMAT). Those skilled in the art can readilyeffect the deposition, thermal and/or plasma techniques in view of thepresent specification and drawing figures.

FIG. 3 shows the beginning of the conversion of the sacrificial film 15from Si3N4 into a SiO₂ layer 16. In FIG. 3, the sacrificial material 15is oxidized in an appropriate environment. Dry oxidation, wet oxidation,or radical oxidation (FIG. 7) may be used to consume the sacrificialmaterial 15. Oxidation/conversion in this embodiment is by means ofradical oxidation (and can be accomplished using conventional plasmabased tooling or in other conventional rapid thermal tooling whichgenerates O* in sufficient quantities). The conversion takes place in atop down fashion with [O] replacing [N] in the dielectric film 15.Radical Oxidation can be realized in the appropriate tool according tothe characterization diagram shown in FIG. 7. Realizing RadicalOxidation according to the present invention would be well understood bythose skilled in the art in view of the present specification anddrawing figures.

In FIG. 4, there is shown a cross section of the final gate oxide layer17. The sacrificial material can be essentially or even completelyconverted to SiO₂. The thickness T of the oxide layer 17 isapproximately 2.4 times the thickness of the sacrificial layer 15, inthe preferred embodiment. During the converting step according to thepreferred embodiment, oxidizing occurs no more than ten (10) angstromsinto the SiGe channel material 13 (i.e. in the direction of theThickness T) and into the Si channel material 14. Even more preferably,none of the SiGe channel material is oxidized. FIG. 4 shows thecompleted SiO₂ gate dielectric. Because the SiO₂ film is generated viathe thermal oxidation of the pre-existing sacrificial film 15, the finaldielectric layer 17 is of a much higher quality relative to the HTOmaterials. Advantages of SiO₂ films generated in this manner (relativeto conventional HTO+DPN+PNA) are 1) better reliability, 2) higherquality SiO₂/channel interfaces (lower Dit levels), and 3) a reductionin the total number of process steps needed to construct the gatedielectric (e.g. elimination of the DPN/PNA post treatment).

DPN is Decoupled Plasma Nitridation.

PNA is Post Nitridation Anneal.

DPN and PNA steps are well known in the semiconductor manufacturingprocess art.

In FIG. 5, final gate stack structures each showing the converted SiO₂dielectric capped with high-k/metal gate stack and polysilicon areillustrated. The illustration is just after conventional “post gateetch,” i.e. PC etch, and before conventional spacer, source/drain, andsilicide formation. The gate materials (HFO₂ or HfSiOX, LaZ03, TiN,Polysilicon) for the N-FET and the gate materials (HfOZ or HfSiOX, TiN,Polysilicon for the P-FET) are deposited using conventional depositiontechniques.

FIG. 6 shows a completed nFET and a completed pFET according to afurther preferred embodiment of the invention with the gate stacks knownin FIG. 5, and conventional spacers, source/drain regions and silicidecaps.

For discussions of various conventional/known techniques for creating anFET and a pFET on a same substrate, see for example:

-   -   U.S. Pat. No. 7,057,216B2 incorporated by reference in its        entirety herein;    -   U.S. Pat. No. 5,547,894 incorporated by reference in its        entirety herein;    -   Fundamentals of Semiconductor Processing Technologies, by Badih        El-Korch (Kluwer Academic Publishers, 1997), and    -   VLSI Technology, by S. M. SZE (McGraw Hill, 1988, ISBN 0-07-062        735-5).

Finally, FIG. 7 (left plot) shows low energy e-beam microprobe data usedto characterize the [N] and [O] content of a sacrificial MLD film as afunction of radical oxidation time. The data was used to illustrate theexcellent process control of the conversion process and to develop asimple empirical model which can be used by those skilled in the art todesign deposited SiO₂ gate dielectrics with different final thicknesses.

Example Tools and Parameters for the preferred embodiment of the presentinvention in a 32 nm Technology Mode include, for example:

MLD Si3N4 deposition is performed at 500 C. Silicon Nitride films aredeposited by exposing wafers to alternating flows of dichlorosilane(DCS) and ammonia plus RF power. Typical conditions are 1 slm of DCS and5 slm of NH3 with 100 W of RF power. The thickness of the layer 15 isdetermined by controlling, e.g., the number of cycles (i.e. number ofthin films deposited).

Radical oxidation (Applied Materials, Inc. tool trade name “ISSG”) isperformed at 900 C, at pressure of 7 T, and with a H2 concentration of5% (500 sccm H2 in 9.5 slm 02). The thickness T of the layer 17 isdetermined by controlling temperature, H2 concentration and/or processtime. All these controls would be well understood by those skilled inthe art, in view of the present specification and drawing figures.

While the invention has been described in terms of embodiments, thoseskilled in the art will recognize that the invention can be practicedwith modifications and in the spirit and scope of the appended claims.For example, the invention can be readily applicable to SOI or othersubstrates.

1. A semiconductor structure, comprising: a substrate having disposedthereon a silicon layer and a silicon germanium layer; an insulatordisposed between the silicon layer and the silicon germanium layer; asilicon nitride film disposed conformally on the silicon layer and thesilicon germanium layer; and a SiO₂ layer disposed on the siliconnitride film.
 2. The structure as claimed in claim 1 wherein the silicongermanium layer has a Ge concentration of approximately 20%.
 3. Thestructure of claim 1 wherein said insulator has an upper most surfacethat is coplanar within an uppermost surface of each of said siliconlayer and said silicon germanium layer.
 4. The structure of claim 1wherein said insulator has one vertical sidewall in direct physicalcontact with a vertical sidewall of said silicon layer and anothervertical sidewall in direct physical contact with a vertical sidewall ofsaid silicon germanium layer.
 5. The structure of claim 1 wherein saidsubstrate comprises bulk silicon.
 6. The structure of claim 1 whereinsaid silicon germanium layer is present at a p-FET region of thesubstrate, and the silicon layer is present at an n-FET region of saidsubstrate.
 7. The structure of claim 1 wherein said silicon germaniumlayer consists essentially of silicon and germanium, and said siliconlayer consists essentially of silicon.
 8. The structure of claim 1wherein said SiO₂layer has a thickness that is greater than a thicknessof said silicon nitride film.
 9. The structure of claim 1 wherein ann-FET gate stack is present on a portion of said SiO₂ layer that islocated atop said silicon layer, and wherein a p-FET gate stack ispresent atop another portion of said SiO₂layer that is located atop saidsilicon germanium layer, said n-FET gate stack is comprised of differentmaterials that said p-FET gate stack.
 10. The structure of claim 9wherein said n-FET gate stack comprises, from bottom to top, HfO₂ orHfSiO_(x), La₂O₃, TiN and polysilicon.
 11. The structure of claim 10wherein said n-FET gate stack comprises, from bottom to top, HfO₂ orHfSiO_(x), TiN and polysilicon.
 12. A semiconductor structure,comprising: a substrate having disposed thereon a silicon layer and asilicon germanium layer; an insulator disposed between the silicon layerand the silicon germanium layer; and a SiO₂layer disposed on the siliconlayer and the silicon germanium layer.
 13. The structure as claimed inclaim 12 wherein the silicon germanium layer has a Ge concentration ofapproximately 20%.
 14. The structure of claim 12 wherein said insulatorhas an upper most surface that is coplanar within an uppermost surfaceof each of said silicon layer and said silicon germanium layer.
 15. Thestructure of claim 12 wherein said insulator has one vertical sidewallin direct physical contact with a vertical sidewall of said siliconlayer and another vertical sidewall in direct physical contact with avertical sidewall of said silicon germanium layer.
 16. The structure ofclaim 12 wherein said substrate comprises bulk silicon.
 17. Thestructure of claim 12 wherein said silicon germanium layer is present ata p-FET region of the substrate, and the silicon layer is present at ann-FET region of said substrate.
 18. The structure of claim 12 whereinsaid silicon germanium layer consists essentially of silicon andgermanium, and said silicon layer consists essentially of silicon. 19.The structure of claim 12 wherein an n-FET gate stack is present on aportion of said SiO₂ layer that is located atop said silicon layer, andwherein a p-FET gate stack is present atop another portion of saidSiO₂layer that is located atop said silicon germanium layer, said n-FETgate stack is comprised of different materials that said p-FET gatestack.
 20. The structure of claim 9 wherein said n-FET gate stackcomprises, from bottom to top, HfO₂ or HfSiO_(x), La₂O₃, TiN andpolysilicon, and said n-FET gate stack comprises, from bottom to top,HfO₂ or HfSiO_(x), TiN and polysilicon.